Feature superfilling in copper electrochemical deposition

• Published in: Journal of the Electrochemical Society 2002, Vol.149 (1), p.C74-C81
• Main Authors: SOUKANE, S, SEN, S, CALE, And T. S
• Format: Article
• Language: English
• Subjects: Applied sciences; Electronics; Exact sciences and technology; Lithography, masks and pattern transfer; Microelectronic fabrication (materials and surfaces technology); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
• ISSN: 0013-4651; 1945-7111
• DOI: 10.1149/1.1426401

We present a finite element-based simulator for electrochemical deposition (ECD) on the scale of features on patterned wafers during integrated circuit (IC) fabrication. The potential, current, and species concentration fields are computed after specifying the dependent variable values above the wafer surface, along with the needed transport and reaction kinetic models. We use this simulator as part of EVOLVE, a topography simulator, to test two chemistry-based deposition rate models that may explain superfilling of micrometer-scale features during IC fabrication. The models both include inhibition, but one includes multisite blocking by the inhibitor. We show that the models work for different cases and conclude that the range of validity of each model is limited. This limitation is to be expected when using simplified models of complex processes such as multiadditive ECD systems; nevertheless, such models can predict the effects of small changes in operating conditions and/or incoming wafer state.