Stacking technology for a space constrained microsystem

In this paper we present a stacking technology for an integrated packaging of an intelligent transducer which is formed by a micromachined silicon transducer and an integrated circuit chip. Transducer and circuitry are stacked on top of each other with an intermediate chip in between. This intermedi...

Full description

Saved in:
Bibliographic Details
Published in:Journal of intelligent material systems and structures 1999-09, Vol.9 (9), p.749-754
Main Authors: Heschel, M, Kuhmann, J F, Bouwstra, S, Amskov, M
Format: Article
Language:English
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper we present a stacking technology for an integrated packaging of an intelligent transducer which is formed by a micromachined silicon transducer and an integrated circuit chip. Transducer and circuitry are stacked on top of each other with an intermediate chip in between. This intermediate chip is made of silicon and carries electrical frontside to backside interconnections through anisotropically etched holes. The electrical feedthrough interconnections are realized by means of lift-off technique. The bonding of the transducer and the intermediate chip is done by fluxless flip chip solder bump bonding. The bonding between the above two-layer stack and the circuit chip is done by conductive adhesive bonding combined with gold studs. We demonstrate the stacking technologies on passive test chips rather than real devices and report on technological details.
ISSN:1045-389X