Impact of gate-poly grain structure on the gate-oxide reliability [CMOS]

Time dependent dielectric breakdown of thin oxides, 1.5 to 5.0 nm has been studied for different gate-poly grain structures. The poly grain was varied by the poly deposition, and the source-drain (S/D) rapid thermal anneal (RTA) conditions. The study, which was done on fully fabricated CMOS devices,...

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Bibliographic Details
Published in:IEEE electron device letters 2002-01, Vol.23 (1), p.22-24
Main Authors: Kamgar, A., Vaidya, H.M., Baumann, F.H., Nakahara, S.
Format: Article
Language:English
Subjects:
Dielectric breakdown
Elasticity
Electric breakdown
Rapid thermal annealing
Rapid thermal processing
Softening
Temperature
Thermal degradation
Viscosity
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Summary:Time dependent dielectric breakdown of thin oxides, 1.5 to 5.0 nm has been studied for different gate-poly grain structures. The poly grain was varied by the poly deposition, and the source-drain (S/D) rapid thermal anneal (RTA) conditions. The study, which was done on fully fabricated CMOS devices, showed substantial reliability degradation in thin gate oxides (below 2.0 nm), when using S/D RTA temperatures above 1000/spl deg/C. The results can be explained in terms of the interface roughness at the gate poly interface induced by the S/D RTA temperature above the viscoelastic point of the SiO/sub 2/. A possible mechanism for the drastic reliability degradation in thin gate oxides, is the protrusion of poly grains into the softening oxide at high temperature.
ISSN:0741-3106
1558-0563
DOI:10.1109/55.974800