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A method for multiple-level logic synthesis based on the simulated annealing algorithm
In this work we address the problem of the synthesis of multiple-level logic functions aimed at achieving area-efficient implementation, using the simulated annealing algorithm (SA). In the quest for a more efficient multiple level synthesis, a two-level optimization with ESPRESSO (T. Sasao, Logic S...
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Published in: | Microelectronics 1997-02, Vol.28 (2), p.143-150 |
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Main Authors: | , , |
Format: | Article |
Language: | English |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | In this work we address the problem of the synthesis of multiple-level logic functions aimed at achieving area-efficient implementation, using the simulated annealing algorithm (SA). In the quest for a more efficient multiple level synthesis, a two-level optimization with ESPRESSO (T. Sasao, Logic Synthesis and Optimization, Kluwer, Amsterdam, 1993) is first carried out. Then, the SA algorithm is applied by means of two new cost functions which yield better results than those obtained with the classical cost functions. The results of the application of this method to the IWLS'93 benchmarks are shown to improve those obtained by the Design Optimizer tool of Synopsys. |
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ISSN: | 1879-2391 0026-2692 1879-2391 |
DOI: | 10.1016/S0026-2692(96)00063-8 |