A method for multiple-level logic synthesis based on the simulated annealing algorithm

In this work we address the problem of the synthesis of multiple-level logic functions aimed at achieving area-efficient implementation, using the simulated annealing algorithm (SA). In the quest for a more efficient multiple level synthesis, a two-level optimization with ESPRESSO (T. Sasao, Logic S...

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Published in:Microelectronics 1997-02, Vol.28 (2), p.143-150
Main Authors: Lanchares, Juan, Hidalgo, JoséIgnacio, Sánchez, Juan Manuel
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Language:English
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description In this work we address the problem of the synthesis of multiple-level logic functions aimed at achieving area-efficient implementation, using the simulated annealing algorithm (SA). In the quest for a more efficient multiple level synthesis, a two-level optimization with ESPRESSO (T. Sasao, Logic Synthesis and Optimization, Kluwer, Amsterdam, 1993) is first carried out. Then, the SA algorithm is applied by means of two new cost functions which yield better results than those obtained with the classical cost functions. The results of the application of this method to the IWLS'93 benchmarks are shown to improve those obtained by the Design Optimizer tool of Synopsys.
doi_str_mv 10.1016/S0026-2692(96)00063-8
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title A method for multiple-level logic synthesis based on the simulated annealing algorithm
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