100 MHz, 0.55 mm super(2), 2 mW, 16-b stacked-CMOS multiplier-accumulator

A 16-b multiplier-accumulator with stacked CMOS has been developed. It can be used for the digital signal processors which, as main parts of multimedia portable terminals, are required to have low power consumption and high processing speed. The stacked-CMOS logic circuit, which has high-speed and l...

Full description

Saved in:
Bibliographic Details
Published in:Proceedings of the Custom Integrated Circuits Conference 1995-01, p.597-600
Main Authors: Igura, Hiroyuki, Izumikawa, Masanori, Furuta, Koichiro, Ito, Hiroshi, Wakabayashi, Hitoshi, Nakajima, Ken, Mogami, Tohru, Horiuchi, Tadahiko, Yamashina, Masakazu
Format: Article
Language:English
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A 16-b multiplier-accumulator with stacked CMOS has been developed. It can be used for the digital signal processors which, as main parts of multimedia portable terminals, are required to have low power consumption and high processing speed. The stacked-CMOS logic circuit, which has high-speed and low-power characteristics, and optimization techniques are employed to attain a low power dissipation value of 2 mW at 100 MHz operation. Its area is 0.55 mm super(2), and the transistor density is two times that of conventional multiplier-accumulators. The fabrication technology is a 0.25- mu m CMOS double layer Al process.
ISSN:0886-5930