Chip set architecture for programmable real time MPEG2 video encoder

This paper describes a chip set architecture for a programmable video encoder based on the MPEG2 main profile at main level (MPqqML). The chip set consists of a Controller-LSI (C-LSI), a macroblock level Pixel Processor-LSI (P-LSI) and a Motion Estimation-LSI (ME-LSI). The chip set combined with syn...

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Main Authors: Matsumura, Tetsuya, Segawa, Hiroshi, Kumaki, Satoshi, Matsuura, Yoshinori, Hanami, Atsuo, Yamaoka, Hiroyasu, Streitenberger, Robert, Nakagawa, Shin-ichi, Ishihara, Kazuya, Kasezawa, Tadashi, Ajioka, Yoshihide, Maeda, Atsushi, Yoshimoto, Masahiko
Format: Conference Proceeding
Language:English
Online Access:Get full text
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Summary:This paper describes a chip set architecture for a programmable video encoder based on the MPEG2 main profile at main level (MPqqML). The chip set consists of a Controller-LSI (C-LSI), a macroblock level Pixel Processor-LSI (P-LSI) and a Motion Estimation-LSI (ME-LSI). The chip set combined with synchronous DRAMs (SDRAM) supports the whole layer processing including rate-control and realizes the real-time encoding for ITU-R-601 resolution video (720x480 pixels at 30 frame/s) with glueless logic. The exhaustive motion estimation capability is scalable up to +-63.5 / +-15.5 in the horizontal / vertical directions. This chip set solution can realize a low cost MPEG2 video encoder system with excellent video quality on a small PC card.
ISSN:0886-5930