Asynchronous design in dynamic CMOS

The design for dynamic CMOS cells that can be used as building blocks in an asynchronous pipeline are discussed in this paper. The proposed circuit elements are variations on TSPC logic using Sutherland's micropipeline structure combined with dual rail logic to detect operation completion. The...

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Bibliographic Details
Main Authors: Ahmed, J., Zaky, S.G.
Format: Conference Proceeding
Language:English
Subjects:
Asynchronous circuits
Circuit testing
Clocks
CMOS logic circuits
Frequency synchronization
Logic circuits
Pipelines
Rails
Signal design
Very large scale integration
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Description
Summary:The design for dynamic CMOS cells that can be used as building blocks in an asynchronous pipeline are discussed in this paper. The proposed circuit elements are variations on TSPC logic using Sutherland's micropipeline structure combined with dual rail logic to detect operation completion. The resulting cell occupies more area than a TSPC cell, but has higher functionality because of the built-in data flow control mechanisms provided by the handshake signaling of the micropipeline structure.
ISSN:0840-7789
2576-7046
DOI:10.1109/CCECE.1997.608275