The microarchitecture of superscalar processors

• Published in: Proceedings of the IEEE 1995-12, Vol.83 (12), p.1609-1624
• Main Authors: Smith, J.E., Sohi, G.S.
• Format: Article
• Language: English
• Subjects: Clocks; Dynamic scheduling; Microarchitecture; Microprocessors; Parallel processing; Pipeline processing; Processor scheduling; Reduced instruction set computing; Registers; Technological innovation
• ISSN: 0018-9219
• DOI: 10.1109/5.476078

Superscalar processing is the latest in along series of innovations aimed at producing ever-faster microprocessors. By exploiting instruction-level parallelism, superscalar processors are capable of executing more than one instruction in a clock cycle. This paper discusses the microarchitecture of superscalar processors. We begin with a discussion of the general problem solved by superscalar processors: converting an ostensibly sequential program into a more parallel one. The principles underlying this process, and the constraints that must be met, are discussed. The paper then provides a description of the specific implementation techniques used in the important phases of superscalar processing. The major phases include: (1) instruction fetching and conditional branch processing, (2) the determination of data dependences involving register values, (3) the initiation, or issuing, of instructions for parallel execution, (4) the communication of data values through memory via loads and stores, and (5) committing the process state in correct order so that precise interrupts can be supported. Examples of recent superscalar microprocessors, the MIPS R10000, the DEC 21164, and the AMD K5 are used to illustrate a variety of superscalar methods.