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Influence of rapid thermal and low temperature processing on the electrical properties of polysilicon thin film transistors

In this paper rapid thermal processing (RTP) is studied for the crystallization and oxidation of deposited silicon layers. The purpose is to present and compare the results obtained by RTP, low temperature processing (LTP), or a combination of both, for the fabrication of polycrystalline silicon thi...

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Bibliographic Details
Published in:IEEE transactions on semiconductor manufacturing 1995-08, Vol.8 (3), p.298-303
Main Authors: Campo, E., Scheid, E., Bielle-Daspet, D., Guillemet, J.-P.
Format: Article
Language:English
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Summary:In this paper rapid thermal processing (RTP) is studied for the crystallization and oxidation of deposited silicon layers. The purpose is to present and compare the results obtained by RTP, low temperature processing (LTP), or a combination of both, for the fabrication of polycrystalline silicon thin film transistors (poly-TFT's). The polysilicon and polyoxide are obtained by low thermal annealing, oxidation (LTA, O) and/or rapid thermal annealing, oxidation (RTA, O) of amorphous silicon films deposited from disilane at a temperature of 465/spl deg/C. For the Si films annealed at 750/spl deg/C or higher, using RTA, the grain average sizes are reduced whereas the electron/hole mobilities are increased. We suggest that there is a correlation between the optical extinction coefficient k (at /spl lambda/=405 nm), the potential barrier height /spl Phi//sub B/ due to the grains, and the field-effect mobility, /spl mu//sub n,p/, of the polysilicon film. This correlation indicates that the polysilicon film electrical properties depend not only on the grain size, but also on the crystalline quality of the grains. Moreover, it appears that the large amount of crystalline defects remaining in the so-called "grains" of the films annealed at 600/spl deg/C (LTA) are partially annihilated when the films are annealed at higher temperatures. With regards to the TFT's electrical characteristics, the work suggests combining RT and LT steps to obtain TFT's with improved electrical performance.< >
ISSN:0894-6507
1558-2345
DOI:10.1109/66.401004