A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator

This paper describes a DRAM macro design from which 2112 configurations up to 32 Mb can be synthesized using a memory generator. The memory generator automatically creates the layout of a DRAM macro in accordance with specification inputs such as memory capacity, address count, bank count, and I/O b...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 1998-11, Vol.33 (11), p.1752-1757
Main Authors: Yabe, T., Miyano, S., Sato, K., Wada, M., Haga, R., Wada, O., Enkaku, M., Hojyo, T., Mimoto, K., Tazawa, M., Ohkubo, T., Numata, K.
Format: Article
Language:English
Subjects:
Application specific integrated circuits
Buffer storage
Circuit testing
Data engineering
Design methodology
Graphics
Large scale integration
Pins
Random access memory
Workstations
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper describes a DRAM macro design from which 2112 configurations up to 32 Mb can be synthesized using a memory generator. The memory generator automatically creates the layout of a DRAM macro in accordance with specification inputs such as memory capacity, address count, bank count, and I/O bits count. An expandable floor layout scheme achieves the macro size comparable to that of handicraft-designed DRAM. The memory generator can customize a configurable redundancy scheme for various macro configurations. Unified testing circuits make it possible to test DRAM macros with more than 500 interface pins in a direct-memory-access mode with 33 test pads. Up to four macros on the same chip can be tested with them. Test chips with 4-Mb DRAM and with 20-Mb DRAM fabricated with 0.35-/spl mu/m technology showed 150-MHz operation.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.726570