Design-for-test methods for stand-alone SRAMS at 1Gb/s/pin and beyond

Design-for-test techniques for wafer test, component test and system-level diagnostics are implemented on stand-alone SRAMs at 1Gb/s/pin. These design-for-test techniques achieve several objectives: improved tester measurement accuracy, higher component yield, and optimal system-level SRAM performan...

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Bibliographic Details
Main Authors: Pilo, Harold, Hansen, Patrick, Lamphier, Steve, Murphy, Chris
Format: Conference Proceeding
Language:English
Online Access:Get full text
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Summary:Design-for-test techniques for wafer test, component test and system-level diagnostics are implemented on stand-alone SRAMs at 1Gb/s/pin. These design-for-test techniques achieve several objectives: improved tester measurement accuracy, higher component yield, and optimal system-level SRAM performance.
ISSN:1089-3539
DOI:10.1109/TEST.2000.894235