Integration of two different gate oxide thicknesses in a 0.6-μm dual voltage mixed signal CMOS process

An approach for integration 3.3 V and 5.0 V transistors with two different gate oxide thickness layers, which eliminates the compromise between the transistor performance and reliability of the gate oxide layers, is described. The approach is robust, since gate oxide layers do not come in contact wi...

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Bibliographic Details
Published in:IEEE transactions on electron devices 1995-01, Vol.42 (1), p.190-192
Main Authors: O, K.K., Yasaitis, J.
Format: Article
Language:English
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Summary:An approach for integration 3.3 V and 5.0 V transistors with two different gate oxide thickness layers, which eliminates the compromise between the transistor performance and reliability of the gate oxide layers, is described. The approach is robust, since gate oxide layers do not come in contact with photoresists, and relatively cost-effective in that it adds only two coarse masking steps. This approach has been demonstrated by integrating 16.5-nm 5.0 V and 10-nm 3.3 V gate oxide layers in a 0.6- mu m mixed signal CMOS process, and demonstrating good 3.3 V and 5.0 V transistor characteristics.
ISSN:0018-9383
DOI:10.1109/16.370017