Low thermal budget high performance 0.25-0.18 mu m merged logic device and dynamic random access memory application

Merged dynamic random access memory (DRAM) with logic technology has been widely investigated because of to its high on-chip memory bandwidth, low power consumption, customized memory size, and small footprint advantages. A low thermal budget 0.25-0.18 mu m embedded DRAM technology has been develope...

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Bibliographic Details
Published in:JPN J APPL PHYS PART 1 REGUL PAP SHORT NOTE REV PAP 2000-01, Vol.39 (5 B), p.2162-2166
Main Authors: Yeh, Wen-Kuan, Lin, Yung-Chang, Chen, Tung-Po, Huang, Cheng-Tung, Chang, Sun-Jay, Lin, Wen-Jeng, Jung, Le-Tien, Chien, Sun-Chieh, Sun, Shin-Wei, Liou, Fou-Tai
Format: Article
Language:English
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Summary:Merged dynamic random access memory (DRAM) with logic technology has been widely investigated because of to its high on-chip memory bandwidth, low power consumption, customized memory size, and small footprint advantages. A low thermal budget 0.25-0.18 mu m embedded DRAM technology has been developed to merge a high-performance logic device and high-density DRAM on the same chip. In this newly developed technology, shallow trench isolation, a triple well, TiSi sub(x) polycide, titanium salicide, a self-aligned contact poly-via and a low thermal budget oxide-nitride-oxide (ONO) as well as Ta sub(2)O sub(5) capacitor dielectrics used for 1 Gbit DRAM design, are being applied. A 32 Mbit synchronous DRAM macro was designed based on this technology and is proposed offered as a drop-in module for embedded DRAM applications.
ISSN:0021-4922