A monolithically integrated Si interband tunneling diode (IBTD)/MOSFET memory for ultra low voltage operation below 0.5 V

• Published in: Superlattices and microstructures 2000-11, Vol.28 (5-6), p.331-337
• Main Authors: Sorada, H., Morita, K., Morimoto, K., Yoshii, S., Uenoyama, T., Ohnaka, K.
• Format: Article
• Language: English
• Subjects: interband tunneling diode, MOSFET, static random access memory
• ISSN: 0749-6036; 1096-3677
• DOI: 10.1006/spmi.2000.0930

A static random access memory (SRAM) cell circuit, constructed using Si interband tunneling diodes (IBTDs) and a metal-oxide-semiconductor field effect transistor (MOSFET), is presented. The Si-IBTD is a negative differential resistance (NDR) device with a tunneling dielectric between a degenerate p+-diffusion layer and an n+-poly-Si electrode. The Si-IBTD was monolithically integrated with the MOSFET on a silicon-on-insulator (SOI) wafer by a novel fabrication process and a compact SRAM cell circuit consisting of two Si-IBTDs and a MOSFET was fabricated. The Si-IBTD shows a full process compatibility with a conventional MOSFET process. Data-read/write operations of this SRAM cell circuit were successfully demonstrated at ultra-low voltage, below 0.5 V, even at room temperature. Simulation results showed that downscaling of the Si-IBTD size was effective for improving the circuit speed. A writing time of the memory cell with a Si-IBTD size of 0.1 μ m2was reduced to 0.8 ns in simulation. The Si-IBTD/MOSFET merged SRAM can be considered one of the most promising candidates for future low-power device applications.