Integration of copper with an organic low-k dielectric in 0.12-μm node interconnect

Today, copper and low-k dielectric are required to reduce interconnect delay and decrease parasitic capacitance. This paper presents the integration of copper with an organic low-k dielectric (k = 2.7) and is focused on the adaptation of the processes required when switching from SiO sub(2) to this...

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Bibliographic Details
Published in:Microelectronic engineering 2002, Vol.60 (1-2), p.119-124
Main Authors: FAYOLLE, M, PASSEMARD, G, ASSOUS, M, LOUIS, D, BEVERINA, A, GOBIL, Y, CLUZEL, J, ARNAUD, L
Format: Article
Language:English
Subjects:
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Summary:Today, copper and low-k dielectric are required to reduce interconnect delay and decrease parasitic capacitance. This paper presents the integration of copper with an organic low-k dielectric (k = 2.7) and is focused on the adaptation of the processes required when switching from SiO sub(2) to this pure organic dielectric. After integration in a dual metal level interconnect for 0.12- mu m generation, it is shown that good electrical results are obtained (100% yield for 0.4- mu m pitch, via resistance < 1 Omega , capacitance reduction of 40% compared to Cu/SiO sub(2) structures), but care must be taken when integrating this low-k material due to its low thermo-mechanical property and sensibility to moisture absorption. copyright 2002 Elsevier Science B.V. All rights reserved.
ISSN:0167-9317
1873-5568
DOI:10.1016/S0167-9317(01)00587-1