Dielectric-Engineered High-Speed, Low-Power, Highly Reliable Charge Trap Flash-Based Synaptic Device for Neuromorphic Computing beyond Inference

• Published in: Nano letters 2023-01, Vol.23 (2), p.451-461
• Main Authors: Kim, Joon Pyo, Kim, Seong Kwang, Park, Seohak, Kuk, Song-hyeon, Kim, Taeyoon, Kim, Bong Ho, Ahn, Seong-Hun, Cho, Yong-Hoon, Jeong, YeonJoo, Choi, Sung-Yool, Kim, Sanghyeon
• Format: Article
• Language: English
• ISSN: 1530-6984; 1530-6992
• DOI: 10.1021/acs.nanolett.2c03453

The coming of the big-data era brought a need for power-efficient computing that cannot be realized in the Von Neumann architecture. Neuromorphic computing which is motivated by the human brain can greatly reduce power consumption through matrix multiplication, and a device that mimics a human synapse plays an important role. However, many synaptic devices suffer from limited linearity and symmetry without using incremental step pulse programming (ISPP). In this work, we demonstrated a charge-trap flash (CTF)-based synaptic transistor using trap-level engineered Al2O3/Ta2O5/Al2O3 gate stack for successful neuromorphic computing. This novel gate stack provided precise control of the conductance with more than 6 bits. We chose the appropriate bias for highly linear and symmetric modulation of conductance and realized it with very short (25 ns) identical pulses at low voltage, resulting in low power consumption and high reliability. Finally, we achieved high learning accuracy in the training of 60000 MNIST images.