Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors

The ability to estimate power consumption during early-stage definition and trade-off studies is a key new methodology enhancement. Opportunities for saving power can be exposed via microarchitecture-level modeling, particularly through clock-gating and dynamic adaptation. In this paper we describe...

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Bibliographic Details
Published in:IEEE MICRO 2000-11, Vol.20 (6), p.26-44
Main Authors: Brooks, D.M., Bose, P., Schuster, S.E., Jacobson, H., Kudva, P.N., Buyuktosunoglu, A., Wellman, J., Zyuban, V., Gupta, M., Cook, P.W.
Format: Article
Language:English
Subjects:
Adaptation
Clocks
Computer architecture
Computer based modeling
Costs
Design engineering
Dynamics
Energy consumption
Estimates
Frequency
Mathematical models
Microarchitecture
Microprocessors
Power consumption
Power dissipation
Process design
Simulators
Switching loss
Tradeoffs
Voltage
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Summary:The ability to estimate power consumption during early-stage definition and trade-off studies is a key new methodology enhancement. Opportunities for saving power can be exposed via microarchitecture-level modeling, particularly through clock-gating and dynamic adaptation. In this paper we describe the approach of using energy-enabled performance simulators in early design. We examine some of the emerging paradigms in processor design and comment on their inherent power-performance characteristics.
ISSN:0272-1732
1937-4143
DOI:10.1109/40.888701