Optimum design in a JFET for minimum generation–recombination noise

Generation–recombination noise caused by the presence of deep level traps in the depletion regions of a junction field effect transistor (JFET) is analyzed. An analytical expression which includes all the elements that influence the process was used. A numerical procedure allowed us to calculate wit...

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Bibliographic Details
Published in:Microelectronics and reliability 2000-11, Vol.40 (11), p.1965-1968
Main Authors: Godoy, A, Jiménez-Tejada, J.A, Palma, A, Carceller, J.E
Format: Article
Language:English
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Summary:Generation–recombination noise caused by the presence of deep level traps in the depletion regions of a junction field effect transistor (JFET) is analyzed. An analytical expression which includes all the elements that influence the process was used. A numerical procedure allowed us to calculate with high precision the magnitudes necessary to evaluate the noise spectral density. The doping profile and gate bias voltage were selected among all the factors involved to analyze their effects on the noise. Important differences were appreciated when uniform and ion-implanted profiles were used for JFET design. Finally, it is shown that the behavior of the noise spectral density as a function of the gate voltage depends on the characteristics of the device.
ISSN:0026-2714
1872-941X
DOI:10.1016/S0026-2714(00)00084-6