Side-Gate Design Optimization of 50 nm MOSFETs with Electrically Induced Source/Drain

50 nm MOSFETs with two poly-Si side-gates are designed. Authors discuss the device structure and its fabrication process. Then, authors investigate the improvement in device performance focusing on short channel effect, current drivability and hot carrier effect with 2-D and two-carrier device simul...

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Bibliographic Details
Published in:Japanese Journal of Applied Physics 2002-04, Vol.41 (Part 1, No. 4B), p.2345-2347
Main Authors: Choi, Woo Young, Choi, Byung Yong, Woo, Dong Soo, Choi, Young Jin, Lee, Jong Duk, Park, Byung-Gook
Format: Article
Language:English
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Summary:50 nm MOSFETs with two poly-Si side-gates are designed. Authors discuss the device structure and its fabrication process. Then, authors investigate the improvement in device performance focusing on short channel effect, current drivability and hot carrier effect with 2-D and two-carrier device simulation. The proposed fabrication method maintains compatibility with conventional MOS technology. Simulation results reveal that when the side-gate length is equal to the main-gate length, the device can be operated in an optimal condition. 8 refs.
ISSN:0021-4922
1347-4065
DOI:10.1143/JJAP.41.2345