Statistical modeling of MOS devices for parametric yield prediction

In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yi...

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Bibliographic Details
Published in:Microelectronics and reliability 2002, Vol.42 (4), p.787-795
Main Authors: Liou, Juin J., Zhang, Qiang, McMacken, John, Thomson, J.Ross, Stiles, Kevin, Layman, Paul
Format: Article
Language:English
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Summary:In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yield) of MOS devices and circuits due to the process variations. To illustrate their applications, the models are applied to the 0.25 μm CMOS technology, and measured data are included in support of the model calculations.
ISSN:0026-2714
1872-941X
DOI:10.1016/S0026-2714(01)00262-1