The Raw microprocessor: a computational fabric for software circuits and general-purpose programs

Wire delay is emerging as the natural limiter to microprocessor scalability. A new architectural approach could solve this problem, as well as deliver unprecedented performance, energy efficiency and cost effectiveness. The Raw microprocessor research prototype uses a scalable instruction set archit...

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Bibliographic Details
Published in:IEEE MICRO 2002-03, Vol.22 (2), p.25-35
Main Authors: Taylor, M.B., Kim, J., Miller, J., Wentzlaff, D., Ghodrat, F., Greenwald, B., Hoffman, H., Johnson, P., Jae-Wook Lee, Lee, W., Ma, A., Saraf, A., Seneski, M., Shnidman, N., Strumpen, V., Frank, M., Amarasinghe, S., Agarwal, A.
Format: Article
Language:English
Subjects:
Architecture
Circuits
Computer architecture
Computer programs
Cost effectiveness
Costs
Delay
Energy efficiency
Fabrics
Integrated circuits
Microprocessors
Raw
Scalability
Software
Software prototyping
Wire
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Summary:Wire delay is emerging as the natural limiter to microprocessor scalability. A new architectural approach could solve this problem, as well as deliver unprecedented performance, energy efficiency and cost effectiveness. The Raw microprocessor research prototype uses a scalable instruction set architecture to attack the emerging wire-delay problem by providing a parallel, software interface to the gate, wire and pin resources of the chip. An architecture that has direct, first-class analogs to all of these physical resources will ultimately let programmers achieve the maximum amount of performance and energy efficiency in the face of wire delay.
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2002.997877