DOUBLE-RECESSED 0.1-MU M-GATE InP HEMTs FOR 40 GBIT/S OPTICAL COMMUNICATION SYSTEMS

Authors developed a double-recessed 0.1-mu m-gate InP-based high electron mobility transistor (DR-HEMT). In this double-recessed-gate structure, the outer-recessed width and the inner-recessed depth are important in terms of the device characteristics. To suppress the maximum electric field strength...

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Bibliographic Details
Published in:Japanese Journal of Applied Physics, Part 1 Part 1, 2003-01, Vol.42 (4B), p.2367-2370
Main Authors: Hoshi, S, Moriguchi, H, Itoh, M, Ohshima, T, Tsunotani, M, Ichioka, T
Format: Article
Language:English
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Summary:Authors developed a double-recessed 0.1-mu m-gate InP-based high electron mobility transistor (DR-HEMT). In this double-recessed-gate structure, the outer-recessed width and the inner-recessed depth are important in terms of the device characteristics. To suppress the maximum electric field strength within the channel region and to reduce the source resistance (Rs), authors performed a device simulation and have obtained the optimum double-recessed gate structure. The DR-HEMT shows a good transconductance over drain conductance gain (gm/gd) of 26 and a high maximum oscillation frequency of 351 GHz because of the improved gd with a small Rs. The propagation delay of a source-coupled field effect transistor logic inverter implemented by DR-HEMTs is as fast as 5.8 ps/gate. Authors applied the DR-HEMT technology to a static 1/2 frequency divider and obtained stable operation up to 43 GHz. 13 refs.
ISSN:0021-4922
DOI:10.1143/jjap.42.2367