Quantum Instruction Set Design for Performance

A quantum instruction set is where quantum hardware and software meet. We develop characterization and compilation techniques for non-Clifford gates to accurately evaluate its designs. Applying these techniques to our fluxonium processor, we show that replacing the iSWAP gate by its square root SQiS...

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Published in:Physical review letters 2023-02, Vol.130 (7), p.070601-070601, Article 070601
Main Authors: Huang, Cupjin, Wang, Tenghui, Wu, Feng, Ding, Dawei, Ye, Qi, Kong, Linghang, Zhang, Fang, Ni, Xiaotong, Song, Zhijun, Shi, Yaoyun, Zhao, Hui-Hai, Deng, Chunqing, Chen, Jianxin
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cited_by cdi_FETCH-LOGICAL-c359t-f2b30bd0ac48ccbc91404532c09619f964484e81693df5e6cedb65efa5bdd0a13
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container_end_page 070601
container_issue 7
container_start_page 070601
container_title Physical review letters
container_volume 130
creator Huang, Cupjin
Wang, Tenghui
Wu, Feng
Ding, Dawei
Ye, Qi
Kong, Linghang
Zhang, Fang
Ni, Xiaotong
Song, Zhijun
Shi, Yaoyun
Zhao, Hui-Hai
Deng, Chunqing
Chen, Jianxin
description A quantum instruction set is where quantum hardware and software meet. We develop characterization and compilation techniques for non-Clifford gates to accurately evaluate its designs. Applying these techniques to our fluxonium processor, we show that replacing the iSWAP gate by its square root SQiSW leads to a significant performance boost at almost no cost. More precisely, on SQiSW we measure a gate fidelity of up to 99.72% and averaging at 99.31%, and realize Haar random two-qubit gates with an average fidelity of 96.38%. This is an average error reduction of 41% for the former and a 50% reduction for the latter compared to using iSWAP on the same processor.
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title Quantum Instruction Set Design for Performance
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