Modeling thermal fatigue cracking in integrated circuits by level sets and the extended finite element method

• Published in: International journal of engineering science 2003-12, Vol.41 (20), p.2381-2410
• Main Authors: Stolarska, M., Chopp, D.L.
• Format: Article
• Language: English
• Subjects: Applied sciences; Computational techniques; Electronics; Exact sciences and technology; Extended finite element method; Fatigue crack growth; Finite-element and galerkin methods; Fracture mechanics (crack, fatigue, damage...); Fracture mechanics, fatigue and cracks; Fundamental areas of phenomenology (including applications); Integrated circuits; Level set method; Materials; Mathematical methods in physics; Physics; Solid mechanics; Structural and continuum mechanics; Thermal cycling
• ISSN: 0020-7225; 1879-2197
• DOI: 10.1016/S0020-7225(03)00217-9

As the demand for faster electronic devices increases, the spacing between interconnect wiring lines within integrated circuits decreases. In this work, an algorithm which couples the level set method with the extended finite element method is used to investigate the effects of the proximity of multiple interconnect lines, multiple cracks, interconnect material, and integrated circuit boundaries on the growth of cracks due to fatigue from thermal cycling. By incorporating enrichment functions to treat displacement discontinuities, these combined methods allow for the crack to pass arbitrarily through elements without the need for remeshing. In the framework of a two-dimensional model where interconnect lines are represented by material inclusions, it is shown that when interconnects are spaced close to one another, cracks can either get quite long or potentially connect with nearby cracks. We illustrate that fatigue cracks approaching a boundary tend to grow along it. It is also shown that the ratio of the Young’s modulus of the interconnect to the Young’s modulus of the substrate affects crack growth as well. The numerical investigation presented here indicates that if the spacing between interconnect lines decreases to a significant degree, the integrity of integrated circuits may be compromised.