Improvement of hot-carrier-reliability by deuterium termination of Si/SiO2 interface defects

We present the improvement of hot-carrier-reliability by deuterium annealing at the temperatures ranging from 430 to 460DGC in the case of CMOS transistors of the design rule of 0.13 *mm. By means of secondary ion mass spectroscopy (SIMS) and ESR measurements, we confirm that this improvement is cau...

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Bibliographic Details
Published in:Applied surface science 2003-06, Vol.216 (1-4), p.347-350
Main Authors: Takahashi, H., Yamada-Kaneta, H.
Format: Article
Language:English
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Summary:We present the improvement of hot-carrier-reliability by deuterium annealing at the temperatures ranging from 430 to 460DGC in the case of CMOS transistors of the design rule of 0.13 *mm. By means of secondary ion mass spectroscopy (SIMS) and ESR measurements, we confirm that this improvement is caused by the termination of the interface defects by deuterium atoms.
ISSN:0169-4332
DOI:10.1016/S0169-4332(03)00422-7