Efficient Test Data Compression and Low Power Scan Testing in SoCs

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan‐in power and test data volume using a modified scan latch reordering...

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Bibliographic Details
Published in:ETRI journal 2003-10, Vol.25 (5), p.321-327
Main Authors: Jung, Jun‐Mo, Chong, Jong‐Wha
Format: Article
Language:English
Subjects:
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
low power scan test
scan test
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
SoC test
test data compression
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Summary:Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan‐in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't‐care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.
ISSN:1225-6463
2233-7326
DOI:10.4218/etrij.03.0303.0017