Device design guidelines for FC-SGT DRAM cells with high soft-error immunity

• Published in: IEEE transactions on electron devices 2005-06, Vol.52 (6), p.1194-1199
• Main Authors: Matsuoka, F., Sakuraba, H., Masuoka, F.
• Format: Article
• Language: English
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Devices; DRAM; DRAM chips; Dynamic random access memory; Electronics; Exact sciences and technology; floating channel type surrounding gate transistor (FC-SGT); floating-body effect; Guidelines; Immunity; Integrated circuit design; Integrated circuits; Integrated circuits by function (including memories and processors); Leakage current; Leakage currents; parasitic bipolar current; Pillars; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; soft error; Soft errors; surrounding gate transistor (SGT)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2005.848860

This paper describes the device design guidelines for floating channel type surrounding gate transistor (FC-SGT) DRAM cells with high soft-error immunity. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional storage capacitor. The cell itself arranges the bit line (BL), storage node, and body region in a silicon pillar vertically and hence, achieves a cell area of 4F/sup 2/ (F: feature size) per bit. A thin-pillar FC-SGT with a metal gate can maintain a low leakage current without using a heavy doping concentration in the body region. Furthermore, as the silicon pillar thickness is reduced, the device enters into the fully depleted operation and as a result can realize excellent switching characteristics. In FC-SGT DRAM cells, the parasitic bipolar current is a major factor that causes soft errors to occur. However, the parasitic bipolar current can be suppressed and its duration can be shortened as the silicon pillar thickness is reduced. As a result, the amount of stored charge lost in the storage capacitor can be effectively decreased by using a thin-pillar FC-SGT. In the case of a 10-nm-thick FC-SGT, the amount lost due to the parasitic bipolar current is decreased to about 28% of that due to the leakage current. Therefore, FC-SGT DRAM is a promising candidate for future nanometer high-density DRAMs having high soft-error immunity.