A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell

• Published in: IEEE microwave and wireless components letters 2005-11, Vol.15 (11), p.754-756
• Main Authors: YANG, Yu-Che, YU, Shih-An, TAO WANG, LU, Shey-Shi
• Format: Article
• Language: English
• Subjects: 1f noise; 50% duty cycle and phase-locked loop (PLL); Applied sciences; Circuit properties; Circuits; Circuits of signal characteristics conditioning (including delay circuits); CMOS technology; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; fractional divider; Integrated circuits; Integrated circuits by function (including memories and processors); Latches; Multiplexing; Phase locked loops; Phase modulation; Phase noise; programmable divider; Quantization; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal to noise ratio
• ISSN: 1531-1309; 2771-957X; 1558-1764; 2771-9588
• DOI: 10.1109/LMWC.2005.858978

A divide-by-1/1.5 divider cell using a dual edge-trigger technique is proposed. Based on this divider cell, a dual-mode programmable divide-by-X circuit is demonstrated in 0.18-μm CMOS technology, where X=P or P.5 in one mode and 2P or 2P+1 in the other mode with P=128-255. When operated in the divide-by-2P/2P+1 mode, this circuit outputs a signal with 50% duty cycle. Theoretically, P can be any arbitrary and programmable integer.