Hardness-by-design approach for 0.15 mum fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity

We designed logic cells hardened for single-event upsets/single-event transients (SEUs/SETs) using hardness-by-design (HBD) methodology on OKI's 0.15 mum fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI) commercial process and evaluated the sample devices. O...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on nuclear science 2005-12, Vol.52 (6), p.2524-2530
Main Authors: Makihara, A, Midorikawa, M, Yamaguchi, T, Iide, Y, Yokose, T, Tsuchiya, Y, Arimitsu, T, Asai, H, Shindou, H, Kuboyama, S, Matsuda, S
Format: Article
Language:English
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We designed logic cells hardened for single-event upsets/single-event transients (SEUs/SETs) using hardness-by-design (HBD) methodology on OKI's 0.15 mum fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI) commercial process and evaluated the sample devices. Our previous work demonstrates that SET-free inverters can be successfully applied as SEU-immune latches. In this paper, the native latches are redesigned using SET-free inverters not only for the inverter loop but also for several types of clock gates (L-SETfree-LoopCK, L-SETfree-LoopCK-SmallArea, and L-SETfree-LoopCK-AddTr.). In addition, the native combinational logic cells are redesigned using SET-free inverters as SET-free NAND and SET-free NOR . Excellent SEU/SET hardness of the HBD latches were achieved up to LET of 64 MeV/(mg/cm/sup 2/).
ISSN:0018-9499
DOI:10.1109/TNS.2005.860716