Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-/spl mu/m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection w...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 2005-06, Vol.40 (6), p.1303-1309
Main Authors: Nonis, R., Da Dalt, N., Palestri, P., Selmi, L.
Format: Article
Language:English
Subjects:
Analog circuits
Applied sciences
Architecture
Circuit optimization
Circuit properties
Circuits
Circuits of signal characteristics conditioning (including delay circuits)
Clock generator
clocking
CMOS
CMOS technology
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Energy consumption
Exact sciences and technology
Gain
Integrated circuit measurements
Integrated circuits
Jitter
Mathematical models
Measurement standards
mixed-mode
Oscillators, resonators, synthetizers
Phase locked loops
phase noise
phase-locked loop (PLL)
Power consumption
Semiconductor device modeling
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
Tuning
voltage-controlled oscillator (VCO)
Voltage-controlled oscillators
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-/spl mu/m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm/sup 2/ and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2005.848037