A multigigabit backplane transceiver core in 0.13-mum CMOS with a power-efficient equalization architecture

• Published in: IEEE journal of solid-state circuits 2005-12, Vol.40 (12), p.2658-2666
• Main Authors: Krishna, K, Yokoyama-Martin, D A, Caffee, A, Jones, C, Loikkanen, M, Parker, J, Segelken, R, Sonntag, J L, Stonick, J, Titus, S, Weinlader, D, Wolfer, S
• Format: Article
• Language: English
• ISSN: 0018-9200
• DOI: 10.1109/JSSC.2005.856574

A binary backplane transceiver core in 0.13-mum dual-gate low-voltage (LV) CMOS, operating at 0.6-9.6 Gb/s with an area of 0.56 mm/sup 2/, is presented. The core uses two taps of transmit preemphasis and an adaptive receive equalization strategy incorporating one tap of unrolled decision feedback equalization (DFE), a linear equalizer, and a bandwidth control mechanism integrated with the receiver calibration circuitry. The output driver uses a cascode structure to achieve a 1.7-V peak-to-peak (p-p) differential output swing with low area and minimal overhead power. The core has extensive optional test features including a built-in bit error rate (BER) tester, voltage margining circuit, and an on-chip receiver sampling scope. The power varies from 152 to 275 mW as the speed varies from 6.25 to 9.6 Gb/s while maintaining a voltage margin of 30 mV at a BER of 10/sup -15/.