Extremely scaled silicon nano-CMOS devices

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is rel...

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Bibliographic Details
Published in:Proceedings of the IEEE 2003-11, Vol.91 (11), p.1860-1873
Main Authors: Chang, L., Yang-kyu Choi, Ha, D., Ranade, P., Shiying Xiong, Bokor, J., Chenming Hu, King, T.J.
Format: Article
Language:English
Subjects:
Circuit optimization
Circuits
CMOS
CMOS technology
Crystal structure
Devices
Electrodes
FinFETs
Gates (circuits)
MOSFET circuits
Nanocomposites
Nanomaterials
Nanoscale devices
Nanostructure
Paper technology
Silicon on insulator technology
Substrates
Transistors
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Description
Summary:Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.
ISSN:0018-9219
1558-2256
DOI:10.1109/JPROC.2003.818336