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Q-factor definition and evaluation for spiral inductors fabricated using wafer-level CSP technology

A novel Q-factor definition and evaluation method are proposed for low-loss high-Q spiral inductors fabricated by using the wafer-level chip-size package (WLP) on silicon substrates, where the copper wiring technology with a polyimide isolation layer is used. In conventional Q-factor evaluation for...

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Bibliographic Details
Published in:IEEE transactions on microwave theory and techniques 2005-10, Vol.53 (10), p.3178-3184
Main Authors: Aoki, Y., Honjo, K.
Format: Article
Language:English
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Summary:A novel Q-factor definition and evaluation method are proposed for low-loss high-Q spiral inductors fabricated by using the wafer-level chip-size package (WLP) on silicon substrates, where the copper wiring technology with a polyimide isolation layer is used. In conventional Q-factor evaluation for inductors, a short-circuited load condition is used, where the Q factor is represented by using Y-parameters as Q=Im{1/Y/sub 11/}/Re{1/Y/sub 11/}. This conventional method provides a Q factor of 20 with 2-5-nH inductance around 3.9 GHz. However, since structures for the spiral inductors are asymmetrical, the short-circuited load condition and short-circuited source condition give different Q values, respectively. The Q-value differences of approximately 100% have often been observed in the WLP. The differences mainly come from differences in loss estimation. In a novel method, a complex conjugate impedance-matching condition is retained both at an input port and an output port of the inductor. The maximum available power gain (G/sub AMAX/) is introduced to evaluate the energy loss in one cycle. This condition provides a unique insertion loss of passive devices. Thus, the difference of the Q factor depends only on the difference of magnetic and electric energy. The difference of the Q value is reduced.
ISSN:0018-9480
1557-9670
DOI:10.1109/TMTT.2005.855147