Drive current enhancement in sub-50 nm CMOS by reduction of SDE resistance with laser thermal process

• Published in: Journal of the Electrochemical Society 2004, Vol.151 (12), p.G895-G899
• Main Authors: YAMAMOTO, Tomonari, GOTO, Ken-Ichi, KUBO, Tomohiro, YUN WANG, LIN, Tim, TALWAR, Somit, KASE, Masataka, SUGII, Toshihiro
• Format: Article
• Language: English
• Subjects: Applied sciences; Condensed matter: electronic structure, electrical, magnetic, and optical properties; Electronic structure and electrical properties of surfaces, interfaces, thin films and low-dimensional structures; Electronic transport in interface structures; Electronics; Exact sciences and technology; Metal-insulator-semiconductor structures (including semiconductor-to-insulator); Physics; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors
• ISSN: 0013-4651; 1945-7111
• DOI: 10.1149/1.1814454

In this paper, we report on the ultrashallow junction profiles and good characteristics of sub-50 nm bulk complementary metal oxide semiconductor (CMOS) devices with n+/p+ source-drain extensions (SDEs) formed by laser thermal processing (UP). By combining UP with preamorphization and strong-dosage dopant-ion implantation, CMOS drive current can be improved without incurring a cost in terms of short-channel deterioration. The SDE-junction depth, SDE overlap length, and sheet resistance were controlled by the energy of preamorphization implantation, and the first two of these parameters were independent of dopant dosage. This allowed us to design strongly activated and abrupt box-like dopant profiles. With this technique, we obtain improvements in drive current of 13 and 8%, respectively, for p- and n-metal oxide semiconductor field effect transistors at Vd = +1 V and Ioff = 100 nA/mum without inducing any short-channel deterioration.