Test chip for the development and evaluation of sensors for measuring stress in metal interconnects

• Published in: IEEE transactions on semiconductor manufacturing 2005-05, Vol.18 (2), p.255-261
• Main Authors: Terry, J.G., Smith, S., Walton, A.J., Gundlach, A.M., Stevenson, J.T.M., Horsfall, A.B., Kai Wang, dos Santos, J.M.M., Soare, S.M., Wright, N.G., O'Neill, A.G., Bull, S.J.
• Format: Article
• Language: English
• Subjects: Aluminum; Applied sciences; Chip formation; Chips; Circuit testing; CMOS; Compressive properties; Compressive stress; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Fabrication; General equipment and techniques; Instruments, apparatus, components and techniques common to several branches of physics and astronomy; Integrated circuit interconnections; Integrated circuit measurements; integrated circuit reliability; Integrated circuit testing; Integrated circuits; Interconnect; metallisation; Microelectronic fabrication (materials and surfaces technology); Physics; reliability; Semiconductor device measurement; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Sensors; Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing; Silicon; stress; Stress measurement; Stresses; Tensile stress
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2005.845096

The development of a new test chip is presented, containing structures for the direct measurement of stress in metallic interconnect layers associated with silicon integrated circuit technology. The rotation of the structures provides a simple method of differentiating between tensile and compressive stress. This test chip design has been used to fabricate working structures allowing the study of stresses in aluminum layers before and after sample sintering. The results are presented together with the design, fabrication, and measurement considerations that have arisen during the research. The problems experienced in removing the sacrificial layer material, necessary to release the structures, are discussed along with potential solutions. The sensor structure is suitable for fabrication within a CMOS facility and its inherent scalability makes it potentially suitable for in-line testing of state-of-the-art processes.