A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique

• Published in: IEEE journal of solid-state circuits 1991-11, Vol.26 (11), p.1593-1599
• Main Authors: Tomita, N., Ohtsuka, N., Miyamoto, J., Imamiya, K., Iyama, Y., Mori, S., Ohsima, Y., Arai, N., Kaneko, Y., Sakagami, E., Yoshikawa, K., Tanaka, S.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit noise; CMOS process; CMOS technology; Delay effects; Electronic equipment; Electronics; EPROM; Exact sciences and technology; Helium; Integrated circuits; Integrated circuits by function (including memories and processors); Read only memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Stress; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.98977

To meet the increasing demand for higher-density and faster EPROMs, a 16-Mb CMOS EPROM has been developed based on 0.6- mu m N-well CMOS technology. In scaled EPROMs, it is important to guarantee device reliability under high-voltage operation during programming. By employing internal programming-voltage reduction and new stress relaxation circuits, it is possible to keep an external programming voltage V/sub pp/ of 12.5 V. The device achieves a 62-ns access time with a 12-mA operating current. A sense-line equalization and data-out latching scheme, made possible by address transition detection (ATD), and a bit-line bias circuit with two types of depletion load led to the fast access time with high noise immunity. This 16-Mb EPROM has pin compatibility with a standard 16-Mb mask-programmable ROM (MROM) and is operative in either word-wide or byte-wide READ mode. Cell size and chip size are 2.2 mu m*1.75 mu m and 7.18 mm*17.39 mm, respectively.< >