A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture

A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2004-03, Vol.39 (3), p.452-462
Main Authors: Zhinian Shu, Ka Lok Lee, Leung, B.H.
Format: Article
Language:English
Subjects:
Bandwidth
Chips
Circuits
CMOS
CMOS technology
Consumption
Dividers
Filters
Frequency synthesizers
Narrowband
Noise
Oscillators
Phase detection
Phase locked loops
Phase noise
Ring oscillators
Voltage-controlled oscillators
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Summary:A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new low-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-/spl mu/m CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of -55 dBc. The chip's output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm/spl deg/.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2003.822896