A 43-Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology

• Published in: IEEE journal of solid-state circuits 2002-12, Vol.37 (12), p.1703-1709
• Main Authors: Nakasha, Y., Suzuki, T., Kano, H., Tsukashima, K., Ohya, A., Sawada, K., Makiyama, K., Takahashi, T., Nishi, M., Hirose, T., Takikawa, M., Watanabe, Y.
• Format: Article
• Language: English
• Subjects: Capacitance; Clocks; Delay; Electron beam lithography; Flip-flops; HEMTs; High electron mobility transistors; Jitter; Multiplexing; Optical fibers; Optical switches; Phase transformations; Semiconductor devices; Timing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2002.804357

This paper describes a full-rate-clock 4:1 multiplexer (MUX) in a 0.13-/spl mu/m InP-based HEMT technology for 40-Gb/s and above optical fiber link systems. To reduce output jitter, the serialized data are retimed at the final stage by a retimer, a D-type flip-flop, which has a symmetric layout with an optimized spacing to the ground that minimizes coupling capacitances. A phase adjuster, composed of an exclusive OR and a delay switch, uses external control signals to change each phase of the serialized data and clock entering the retimer and gives a correct timing for the clock to drive the retimer. A clock distributor with a simple wired splitter divides the clock into two clocks with high gain and low current. The MUX integrates 1355 HEMTs formed using electron beam lithography. A chip mounted in a test module operated at up to 47 Gb/s with a power consumption of 7.9 W for a single supply voltage of -5.2 V.