3-valued trace-based fault simulation of synchronous sequential circuits

An efficient fault simulation algorithm for synchronous sequential circuits is presented. It uses parallel fault simulation with dynamic fault grouping, and combines it with backtracing within certain fanout-free regions and the use of surrogate faults. A backtracing method is developed to handle th...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 1993-09, Vol.12 (9), p.1419-1424
Main Authors: Song, O.Y., Menon, P.R.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit faults
Circuit simulation
Circuit testing
Computational modeling
Computer science
control theory
systems
Computer simulation
Digital circuits
Exact sciences and technology
Fault detection
Integrated circuit testing
Logic
Sequential circuits
Simulation
Software
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Summary:An efficient fault simulation algorithm for synchronous sequential circuits is presented. It uses parallel fault simulation with dynamic fault grouping, and combines it with backtracing within certain fanout-free regions and the use of surrogate faults. A backtracing method is developed to handle the three logic values, 0,1, and X, accurately. The concept of surrogate faults is also extended to represent all nine combinations of fault-free and faulty values. The results of simulating a set of benchmark sequential circuits show that reductions in execution time of 7-54% were obtained by the use of backtracing and surrogate faults compared to the well-known method, PROOFS.< >
ISSN:0278-0070
1937-4151
DOI:10.1109/43.240090