A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces

A 64 K CMOS RAM with emitter-coupled logic (ECL) interfaces having access times of 6.2 ns at room temperature and with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature, is presented. The CMOS processes feature a 0.5 mu m L/sub eff/, self...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1989-08, Vol.24 (4), p.859-868
Main Authors: Chappell, T.I., Schuster, S.E., Chappell, B.A., Allan, J.W., Sun, J.Y., Klepner, S.P., Franch, S.P., Greier, P.F., Restle, P.J.
Format: Article
Language:English
Subjects:
BiCMOS integrated circuits
CMOS process
CMOS technology
Driver circuits
Nitrogen
Power supplies
Read-write memory
Signal design
Temperature
Time measurement
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Summary:A 64 K CMOS RAM with emitter-coupled logic (ECL) interfaces having access times of 6.2 ns at room temperature and with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature, is presented. The CMOS processes feature a 0.5 mu m L/sub eff/, self-aligned TiSi/sub 2/ double-level metal, and an average minimum feature size of 1.35 mu m. Circuits keyed to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation including circuit-device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits are discussed.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.34062