A 16K CMOS PROM with polysilicon fusible links

A 16K synchronous CMOS PROM with polysilicon fusible links and a 2K-word by 8-bit organization is described. The memory cell makes use of the vertical bipolar NPN that is inherent in the p-well CMOS process. An advanced polysilicon fuse process is used for the fusible links. The technology incorpora...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1983-10, Vol.18 (5), p.562-567
Main Author: Metzger, L.R.
Format: Article
Language:English
Subjects:
CMOS process
CMOS technology
Current supplies
Epitaxial layers
EPROM
Equivalent circuits
Fuses
Material storage
PROM
Voltage
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Description
Summary:A 16K synchronous CMOS PROM with polysilicon fusible links and a 2K-word by 8-bit organization is described. The memory cell makes use of the vertical bipolar NPN that is inherent in the p-well CMOS process. An advanced polysilicon fuse process is used for the fusible links. The technology incorporates use of an epitaxial layer that eliminates latchup potential at programming voltages. A special verify mode is used to detect marginally blown fuses during programming. The design features a typical access time of 50 ns and 1-/spl mu/A standby current.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1983.1051994