A 20 ns 64K CMOS static RAM

A 64K-word by 1-bit CMOS static RAM with a 20-ns typical address access time and 70-mW active power dissipation is described. Third-generation CMOS (Hi-CMOSIII) technology is also described. In this technology, n-channel and p-channel MOS transistors having 1.3 /spl mu/m typical gate length and 1.3...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 1984-12, Vol.19 (6), p.1008-1013
Main Authors: Minato, O., Masuhara, T., Sasaki, T., Matsumoto, K., Sakai, Y., Hayashida, T.
Format: Article
Language:English
Subjects:
Bipolar transistors
Capacitance
Circuit optimization
CMOS technology
Cutoff frequency
Flip-flops
MOSFETs
Random access memory
Read-write memory
Substrates
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A 64K-word by 1-bit CMOS static RAM with a 20-ns typical address access time and 70-mW active power dissipation is described. Third-generation CMOS (Hi-CMOSIII) technology is also described. In this technology, n-channel and p-channel MOS transistors having 1.3 /spl mu/m typical gate length and 1.3 /spl mu/m design rule are used. Good RAM performance is achieved by use of a pulsed-word-line technique and double p-well bipolar-CMOS circuitry.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1984.1052259