A 4-GHz clock system for a high-performance system-on-a-chip design

• Published in: IEEE journal of solid-state circuits 2001-11, Vol.36 (11), p.1693-1698
• Main Authors: Ingino, J.M., von Kaenel, V.R.
• Format: Article
• Language: English
• Subjects: Active filters; Analog circuits; Circuit noise; Clocks; CMOS technology; Design engineering; Digital; Frequency; High speed; Jitter; Noise; Noise levels; Phase locked loops; Phase noise; Rejection; System-on-a-chip
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.962289

A digital system's clocks must have not only low jitter, but also well-controlled duty cycles in order to facilitate versatile clocking techniques. Power-supply noise is often the most common and dominant source of jitter on a phase-locked loop's (PLL) output clock. Jitter can be minimized by regulating the supply to the PLL's noise-sensitive analog circuit blocks in order to filter out supply noise. This paper introduces a PLL-based clock generator intended for use in a high-speed highly integrated system-on-a-chip design. The generator produces clocks with accurate duty cycles and phase relationships by means of a high-speed divider design. The PLL also achieves a power-supply rejection ratio (PSRR) greater than 40 dB while operating at frequencies exceeding 4 GHz. The high level of noise rejection exceeds that of earlier designs by using a combination of both passive and active filtering of the PLL's analog supply voltage. The PLL system has been integrated in a 0.15-/spl mu/m single-poly 5-metal digital CMOS technology. The measured performance indicates that at a 4-GHz output frequency the circuit achieves a PSRR greater than 40 dB. The peak cycle-to-cycle jitter is 25 ps at 700 MHz and a 2.8-GHz VCO frequency with a 500-mV step on the regulator's 3.3-V supply. The total power dissipated by the prototype is 130 mW and its active area is 1.48/spl times/1.00 mm/sup 2/.