A 100-MHz 2-D discrete cosine transform core processor

• Published in: IEEE journal of solid-state circuits 1992-04, Vol.27 (4), p.492-499
• Main Authors: Uramoto, S., Inoue, Y., Takabatake, A., Takeda, J., Yamashita, H., Terane, H., Yoshimoto, M.
• Format: Article
• Language: English
• Subjects: Applied sciences; Arithmetic; Circuits; CMOS technology; Discrete cosine transforms; Electronics; Exact sciences and technology; Hardware; HDTV; Image coding; Integrated circuits; Integrated circuits by function (including memories and processors); Read only memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal processing; Transform coding
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.126536

A 100-MHz two-dimensional discrete cosine transform (DCT) core processor applicable to the real-time processing of HDTV signals is described. An excellent architecture utilizing a fast DCT algorithm and multiplier accumulators based on distributed arithmetic have contributed to reducing the hardware amount and to enhancing the speed performance. A layout scheme with a column-interleaved memory and a new ROM circuit are introduced for the efficient implementation of memory-based signal processing circuits. Furthermore, mean values of errors generated in the core were minimized to enhance the computational accuracy with the word-length constraints. Consequently, it features the fastest operating speed and the smallest area with sufficient accuracy to satisfy the specifications in CCITT recommendation H.261. The core integrates about 102 K transistors and occupies 21 mm/sup 2/ using 0.8- mu m double-metal CMOS technology.< >