Bipolar transistor selected P-channel flash memory cell technology

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but a...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2001-05, Vol.48 (5), p.863-867
Main Authors: Ohnakado, T., Ajika, N., Satoh, S.
Format: Article
Language:English
Subjects:
Amplification
Bipolar transistors
CMOS memory integrated circuits
Devices
Flash memory (computers)
Semiconductor devices
Transistors
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Summary:A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory.
ISSN:0018-9383
1557-9646
DOI:10.1109/16.918232