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Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory
With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n/sup -/ junction with n/sup +/ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robust...
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Published in: | IEEE transactions on electronics packaging manufacturing 2000-10, Vol.23 (4), p.246-254 |
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Main Authors: | , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites |
Online Access: | Get full text |
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Summary: | With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n/sup -/ junction with n/sup +/ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness. |
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ISSN: | 1521-334X 1558-0822 |
DOI: | 10.1109/6104.895068 |