Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n/sup -/ junction with n/sup +/ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robust...

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Published in:IEEE transactions on electronics packaging manufacturing 2000-10, Vol.23 (4), p.246-254
Main Authors: Ikehashi, T., Imamiya, K., Sakui, K.
Format: Article
Language:English
Subjects:
Circuit design
Circuit simulation
Circuits
CMOS process
Contact holes
Design methodology
Devices
Electronics packaging
Electrostatic discharge
Flash memory (computers)
Isolation technology
Large scale integration
MOS devices
MOSFET circuits
Protection
Robustness
Simulation
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creator Ikehashi, T.
Imamiya, K.
Sakui, K.
description With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n/sup -/ junction with n/sup +/ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.
doi_str_mv 10.1109/6104.895068
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fullrecord <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_proquest_miscellaneous_28233214</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>895068</ieee_id><sourcerecordid>2434065711</sourcerecordid><originalsourceid>FETCH-LOGICAL-c231t-1d456235134b60675f1e57d78aac142de3dee79e4ebf75bad3b570acc85f15a93</originalsourceid><addsrcrecordid>eNp90c1LwzAYBvAgCs7pyZun4EEE6cxnmx5lmzqY87AJnixp-nbraJeZtIf997Z0ePDgKYH3x5O8PAhdUzKilMSPISVipGJJQnWCBlRKFRDF2Gl3ZzTgXHyeowvvt4RQIRkboK8J-GK9wxXUG5vZ0q4P2OZYY2fTxtd4upzgvbM1mLqwO2wKZ5qixrl1eLmadSMD3mMmQ_yW4sXTYoLzUvtNG1hZd7hEZ7kuPVwdzyH6eJ6uxq_B_P1lNn6aB4ZxWgc0EzJkXFIu0pCEkcwpyCiLlNaGCpYBzwCiGASkeSRTnfFURkQbo1opdcyH6K7PbT_03YCvk6rwBspS78A2PmGKcc6oaOH9v5ASxlTMIkVbevuHbm3jdu0aiVKSEMnC7uGHHhlnvXeQJ3tXVNod2qSk6yTpOkn6Tlp90-sCAH7lcfgD0daEgw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>885005269</pqid></control><display><type>article</type><title>Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory</title><source>IEEE Xplore (Online service)</source><creator>Ikehashi, T. ; Imamiya, K. ; Sakui, K.</creator><creatorcontrib>Ikehashi, T. ; Imamiya, K. ; Sakui, K.</creatorcontrib><description>With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n/sup -/ junction with n/sup +/ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.</description><identifier>ISSN: 1521-334X</identifier><identifier>EISSN: 1558-0822</identifier><identifier>DOI: 10.1109/6104.895068</identifier><identifier>CODEN: ITEPFL</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Circuit design ; Circuit simulation ; Circuits ; CMOS process ; Contact holes ; Design methodology ; Devices ; Electronics packaging ; Electrostatic discharge ; Flash memory (computers) ; Isolation technology ; Large scale integration ; MOS devices ; MOSFET circuits ; Protection ; Robustness ; Simulation</subject><ispartof>IEEE transactions on electronics packaging manufacturing, 2000-10, Vol.23 (4), p.246-254</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2000</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c231t-1d456235134b60675f1e57d78aac142de3dee79e4ebf75bad3b570acc85f15a93</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/895068$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,27903,27904,54775</link.rule.ids></links><search><creatorcontrib>Ikehashi, T.</creatorcontrib><creatorcontrib>Imamiya, K.</creatorcontrib><creatorcontrib>Sakui, K.</creatorcontrib><title>Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory</title><title>IEEE transactions on electronics packaging manufacturing</title><addtitle>TEPM</addtitle><description>With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n/sup -/ junction with n/sup +/ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.</description><subject>Circuit design</subject><subject>Circuit simulation</subject><subject>Circuits</subject><subject>CMOS process</subject><subject>Contact holes</subject><subject>Design methodology</subject><subject>Devices</subject><subject>Electronics packaging</subject><subject>Electrostatic discharge</subject><subject>Flash memory (computers)</subject><subject>Isolation technology</subject><subject>Large scale integration</subject><subject>MOS devices</subject><subject>MOSFET circuits</subject><subject>Protection</subject><subject>Robustness</subject><subject>Simulation</subject><issn>1521-334X</issn><issn>1558-0822</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2000</creationdate><recordtype>article</recordtype><recordid>eNp90c1LwzAYBvAgCs7pyZun4EEE6cxnmx5lmzqY87AJnixp-nbraJeZtIf997Z0ePDgKYH3x5O8PAhdUzKilMSPISVipGJJQnWCBlRKFRDF2Gl3ZzTgXHyeowvvt4RQIRkboK8J-GK9wxXUG5vZ0q4P2OZYY2fTxtd4upzgvbM1mLqwO2wKZ5qixrl1eLmadSMD3mMmQ_yW4sXTYoLzUvtNG1hZd7hEZ7kuPVwdzyH6eJ6uxq_B_P1lNn6aB4ZxWgc0EzJkXFIu0pCEkcwpyCiLlNaGCpYBzwCiGASkeSRTnfFURkQbo1opdcyH6K7PbT_03YCvk6rwBspS78A2PmGKcc6oaOH9v5ASxlTMIkVbevuHbm3jdu0aiVKSEMnC7uGHHhlnvXeQJ3tXVNod2qSk6yTpOkn6Tlp90-sCAH7lcfgD0daEgw</recordid><startdate>20001001</startdate><enddate>20001001</enddate><creator>Ikehashi, T.</creator><creator>Imamiya, K.</creator><creator>Sakui, K.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>L7M</scope></search><sort><creationdate>20001001</creationdate><title>Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory</title><author>Ikehashi, T. ; Imamiya, K. ; Sakui, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c231t-1d456235134b60675f1e57d78aac142de3dee79e4ebf75bad3b570acc85f15a93</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2000</creationdate><topic>Circuit design</topic><topic>Circuit simulation</topic><topic>Circuits</topic><topic>CMOS process</topic><topic>Contact holes</topic><topic>Design methodology</topic><topic>Devices</topic><topic>Electronics packaging</topic><topic>Electrostatic discharge</topic><topic>Flash memory (computers)</topic><topic>Isolation technology</topic><topic>Large scale integration</topic><topic>MOS devices</topic><topic>MOSFET circuits</topic><topic>Protection</topic><topic>Robustness</topic><topic>Simulation</topic><toplevel>online_resources</toplevel><creatorcontrib>Ikehashi, T.</creatorcontrib><creatorcontrib>Imamiya, K.</creatorcontrib><creatorcontrib>Sakui, K.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology &amp; Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electronics packaging manufacturing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Ikehashi, T.</au><au>Imamiya, K.</au><au>Sakui, K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory</atitle><jtitle>IEEE transactions on electronics packaging manufacturing</jtitle><stitle>TEPM</stitle><date>2000-10-01</date><risdate>2000</risdate><volume>23</volume><issue>4</issue><spage>246</spage><epage>254</epage><pages>246-254</pages><issn>1521-334X</issn><eissn>1558-0822</eissn><coden>ITEPFL</coden><abstract>With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n/sup -/ junction with n/sup +/ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/6104.895068</doi><tpages>9</tpages></addata></record>
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source IEEE Xplore (Online service)
subjects Circuit design
Circuit simulation
Circuits
CMOS process
Contact holes
Design methodology
Devices
Electronics packaging
Electrostatic discharge
Flash memory (computers)
Isolation technology
Large scale integration
MOS devices
MOSFET circuits
Protection
Robustness
Simulation
title Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T10%3A13%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Design%20methodology%20of%20a%20robust%20ESD%20protection%20circuit%20for%20STI%20process%20256%20Mb%20NAND%20flash%20memory&rft.jtitle=IEEE%20transactions%20on%20electronics%20packaging%20manufacturing&rft.au=Ikehashi,%20T.&rft.date=2000-10-01&rft.volume=23&rft.issue=4&rft.spage=246&rft.epage=254&rft.pages=246-254&rft.issn=1521-334X&rft.eissn=1558-0822&rft.coden=ITEPFL&rft_id=info:doi/10.1109/6104.895068&rft_dat=%3Cproquest_ieee_%3E2434065711%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c231t-1d456235134b60675f1e57d78aac142de3dee79e4ebf75bad3b570acc85f15a93%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=885005269&rft_id=info:pmid/&rft_ieee_id=895068&rfr_iscdi=true