Design of CMOS circuits for stuck-open fault testability

A CMOS design that offers highly testable CMOS circuits is presented. The design requires a minimal amount of extra hardware for testing. The test phase for the proposed design is simple and uses a single test vector to detect a fault. The design offers the detection of transistor stuck-open faults...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1991-01, Vol.26 (1), p.58-61
Main Authors: Jayasumana, A.P., Malaiya, Y.K., Rajsuman, R.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit faults
Circuit testing
Design. Technologies. Operation analysis. Testing
Electrical fault detection
Electronics
Exact sciences and technology
Fault detection
FETs
Hardware
Helium
Integrated circuits
Logic testing
Robustness
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Timing
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Description
Summary:A CMOS design that offers highly testable CMOS circuits is presented. The design requires a minimal amount of extra hardware for testing. The test phase for the proposed design is simple and uses a single test vector to detect a fault. The design offers the detection of transistor stuck-open faults deterministically. In this design, the tests are not invalidated due to timing skews/delays, glitches, or charge redistribution among the internal nodes.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.65711