Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with d...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2001-04, Vol.9 (2), p.390-394
Main Authors: Pant, P., Roy, R.K., Chattejee, A.
Format: Article
Language:English
Subjects:
Applied sciences
CMOS digital integrated circuits
CMOS logic circuits
CMOS process
Consumer electronics
Design. Technologies. Operation analysis. Testing
Electronics
Energy consumption
Exact sciences and technology
Integrated circuits
Logic devices
Power dissipation
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Threshold voltage
Very large scale integration
Wireless communication
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Summary:We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of a circuit by as much as 50%.
ISSN:1063-8210
1557-9999
DOI:10.1109/92.924061